TFT substrate with low contact resistance and damage resistant terminals

ABSTRACT

A conductive film made of Al or alloy containing Al as a main component is formed on an underlying substrate. An upper conductive film is disposed on the conductive film. A first opening is formed through the upper conductive film. An insulating film is disposed on the upper conductive film. A second opening is formed through the insulating film. An inner wall of the second opening is retreated from an inner wall of the first opening. An ITO film is formed covering a partial upper surface of the insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of the upper conductive film at a region inside of the second opening. Good electrical contact between an Al or Al alloy film and an ITO film can be established and productivity can be improved.

[0001] This application is based on Japanese patent applications HEI10-5 243449 filed on Aug. 28, 1998 and HEI 11-22501 filed on Jan. 29,1999, the whole contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] a) Field of the Invention

[0003] The present invention relates to an indium tin oxide (ITO) filmcontact structure, a thin film transistor (TFT) substrate, and itsmanufacture, and more particularly to a structure for electricallycontacting an ITO film with an Al alloy film, a TFT substrate havingsuch a contact structure, a method of manufacturing such a TFTsubstrate, and a TFT substrate with external connection terminals.

[0004] b) Description of the Related Art

[0005]FIG. 8 is a cross sectional view of a TFT and a pixel electrode ofa conventional active matrix type liquid crystal display panel. TFT'sare disposed in a matrix pattern on an image display area of a glasssubstrate 1, and external terminals 3 are disposed in a border areaaround the image display area. FIG. 8 shows a single TFT 10 among aplurality of TFT's.

[0006] TFT 10 is constituted of a gate electrode 11, a channel layer 12,a channel protective film 18, a source electrode 13S, and a drainelectrode 13D. The gate electrode 11 is disposed on the surface of theglass substrate 1. A first insulating film 4 is formed on the glasssubstrate 1, covering the gate electrode 11, and the channel layer 12 isformed on the first insulating film 4, overriding the gate electrode 11.The channel protective film 18 protects a surface of the channel layer12 over the gate electrode 11.

[0007] Partial surfaces of the channel layer 12 on both sides of thegate electrode 11 are covered with the source electrode 13S and drainelectrode 13D. Each of the source electrode 13S and drain electrode 13Dhas a four-layer structure having an amorphous silicon film 14, a lowerTi film 15, an Al film 16, and an upper Ti film 17 laminated in thisorder from the bottom.

[0008] A second insulating film 30 is formed on the first insulatingfilm 4, and covers TFT 10. An opening 31 is formed through the secondinsulating film 30 in an area corresponding to the source electrode 13S.An indium tin oxide (ITO) film 35 is formed on the inner surface of theopening 31 and on a partial surface of the second insulating film 30.The ITO film 35 is connected to the source electrode 13S at the bottomof the opening 31.

[0009] In the border area, the external terminal 3 is covered with thefirst and second insulating films 4 and 30. An opening 40 is formedthrough these two first and second insulating films 4 and 30, theopening 40 exposing a partial top surface of the external terminal 3.

[0010] The lower Ti film 15 inserted between the Al film 16 andamorphous silicon layer 14 prevents the element performance from beingdegraded by Al diffusion. If the Al film 16 is directly contacted withthe ITO film 35, a contact resistance is high. The upper Ti film 17inserted between the Al film 16 and ITO film 35 lowers the contactresistance.

[0011] In the conventional active matrix type liquid crystal displaypanel shown in FIG. 8, the openings 31 and 40 are formed at the sametime. The depth of the opening 31 corresponds to the thickness of thesecond insulating film 30, whereas the depth of the opening 40corresponds to a total thickness of the first and second insulatingfilms 4 and 30. Therefore, while the first insulating film 4 is etchedto form the opening 40, the upper Ti film 17 on the bottom of theopening 31 is exposed to the etching atmosphere. If the upper Ti film 17on the bottom of the opening 31 is completely removed, the ITO film 35directly contacts the Al film so that the contact resistance becomeshigh.

[0012] In order to leave the upper Ti film 17 on the bottom of theopening 31 with good reproductivity, it is necessary to make the upperTi film 17 sufficiently thick. For example, it is preferable to make theupper Ti film 17 have a thickness of 100 nm or more. As the upper Tifilm 17 is made thick, it takes a longer time to etch and pattern thesource and drain electrodes 13S and 13D, so that improvement onproductivity is hindered.

[0013]FIG. 9 is a cross sectional view of a terminal formed on thesurface of a conventional TFT substrate. A gate insulating film 4 coversthe surface of a glass substrate 1. An amorphous silicon film 12 a isformed on a partial surface area of the gate insulating film 4. Aterminal 21 a is formed on the amorphous silicon film 12 a. The terminal21 a has a lamination structure of an amorphous silicon film 14 a, alower Ti film 15 a, an Al film 16 a, and an upper Ti film 17 a,sequentially laminated in this order. In the pixel area, the amorphoussilicon film 12 a constitutes a channel layer of a TFT, and the fourlayers from the amorphous silicon film 14 a to the upper Ti film 17 aconstitute a source electrode, a drain electrode, and a drain bus line,respectively of TFT.

[0014] A second insulating film (protective insulating film) 30 isformed on the first insulating film (gate insulating film) 4, coveringthe lamination structure from the amorphous silicon film 12 a to theupper Ti film 17 a. A contact hole 32 is formed through the protectiveinsulating film 30, in an area above the terminal 21 a. A terminalprotective conductive film 35 a made of indium tin oxide (ITO) coversthe inner surface of the contact hole 32 and the nearby surface of theprotective insulating film 30. The terminal protective conductive film35 a prevents corrosion and damages of the terminal 21 a. The terminalprotective conductive film 35 a is formed at the same time when a pixelelectrode is formed in the pixel area.

[0015] A probe is made in contact with the surface of the terminalprotective conductive film 35 a to conduct a conduction test and aninsulation test. A terminal for a tape automatic bonding (TAB) terminalhas a similar structure to that shown in FIG. 9.

[0016] In the past, there was a case that when a probe was made incontact with the surface of the terminal protective conductive film 35 ashown in FIG. 9, the probe broke through the terminal protectiveconductive film 35 a and gave damages to the underlying upper Ti film 17a and Al film 16 a.

SUMMARY OF THE INVENTION

[0017] It is an object of the present invention to provide an ITO filmcontact structure capable of realizing good electrical contact betweenAl or Al alloy film and an ITO film, and improving productivity.

[0018] It is another object of the present invention to provide a TFTsubstrate and its manufacture method capable of realizing goodelectrical contact between Al or Al alloy film and an ITO film, andimproving productivity.

[0019] It is another object of the present invention to provide a TFTsubstrate having a high connection reliability terminal structure hardto be damaged when a probe is made in contact with this structure.

[0020] According to one aspect of the present invention, there isprovided an ITO film contact structure comprising: a conductive filmmade of Al or alloy containing Al as a main component; an upperconductive film disposed on said conductive film, formed with a firstopening, and made of a material different from Al; an insulating filmdisposed on said upper conductive film and formed with a second opening,an inner wall of the second opening being retreated from an inner wallof the first opening; and an ITO film covering a partial upper surfaceof said insulating film and inner surfaces of the first and secondopenings, and contacting a partial upper surface of said upperconductive film at a region defining a part of the inner wall of thesecond opening.

[0021] Since the ITO film is connected via the upper conductive film tothe conductive film, good electrical contact between the ITO film andconductive film can be established.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a cross sectional view of a TFT substrate according to afirst embodiment of the invention.

[0023]FIG. 2 is a graph showing a relation between an etching pressureand a lateral etching amount of a silicon nitride (SiN) film.

[0024]FIG. 3 is a plan view of a TFT substrate according to anembodiment of the invention.

[0025]FIGS. 4A and 4B are cross sectional views of inspection terminalsformed on TFT substrates according to a second embodiment of theinvention.

[0026]FIG. 5 is a cross sectional view of an inspection drain terminalaccording to the second embodiment of the invention.

[0027]FIGS. 6A and 6B are plan views of inspection drain terminalsaccording to modifications of the second embodiment of the invention.

[0028]FIG. 7 is a cross sectional view of a LCD panel with a TFTsubstrate.

[0029]FIG. 8 is a cross sectional view of a conventional TFT substrate.

[0030]FIG. 9 is a cross sectional view of a conventional inspectionterminal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031]FIG. 1 is a cross sectional view of a TFT substrate according toan embodiment of the invention. TFT's 10 are disposed in a matrixpattern on an image display area of a glass substrate 1, and externalterminals 3 are disposed in a border area around the image display area.FIG. 1 shows a single TFT 10 among a plurality of TFT's.

[0032] TFT 10 is constituted of a gate electrode 11, a channel layer 12,a channel protective film 18, a source electrode 13S, and a drainelectrode 13D. The gate electrode 11 made of Cr (or Al alloy, Al/Tilamination or the like) and having a thickness of 150 nm is disposed onthe surface of the glass substrate 1. Each gate electrode 11 iscontinuous with a control line extending in a row direction (not shownin FIG. 1). The control line extends to the border area and iscontinuous with the external terminal 3.

[0033] A first insulating film 4 made of SiN and having a thickness of400 nm is formed on the glass substrate 1, the film 4 covering the gateelectrode 11. The channel layer 12 made of amorphous silicon and havinga thickness of 30 nm is formed on the first insulating film 4, thechannel layer 12 overriding the gate electrode 11.

[0034] The channel protective film 18 protects a partial surface of thechannel layer 12 over the gate electrode 11. The channel protective film18 is made of SiN and has a thickness of 120 nm.

[0035] Surface areas of the channel layer 12 on both sides of the gateelectrode 11 are covered with the source electrode 13S and drainelectrode 13D. Each of the source electrode 13S and drain electrode 13Dhas a four-layer structure having an n⁺-type amorphous silicon film 14,a lower Ti film 15, an Al film 16, and an upper Ti film 17 laminated inthis order from the bottom. The n⁺-type amorphous silicon film 14 is 30nm in thickness, the lower and upper Ti films 15 and 17 are 20 nm inthickness, and the Al film 16 is 100 nm in thickness. An opening 31 a isformed through the upper Ti film 17 of the source electrode 13S.

[0036] A second insulating film 30 made of SiN and having a thickness of300 nm is formed on the first insulating film 4, the film 30 coveringTFT 10. An opening 31 b is formed through the second insulating film 30in an area corresponding to the opening 31 a. When looking along adirection normal to the substrate, the circumference of the opening 31 bis located outside the circumference of the opening 31 a. An ITO film 35having a thickness of 70 nm is formed on the inner surfaces of theopenings 31 a and 31 b and on a partial surface of the second insulatingfilm 30.

[0037] In the border area, the external terminal 3 is covered with thefirst and second insulating films 4 and 30. An opening 40 is formedthrough these two first and second insulating films 4 and 30, theopening 40 exposing a partial top surface of the external terminal 3.The inner wall of the opening 40 in the second insulating film 30 isretreated from the inner wall of the opening in the first insulatingfilm 4. Namely, a step is formed at the position corresponding to theinterface between the first and second insulating films 4 and 30.

[0038] In the embodiment shown in FIG. 1, the ITO film 35 contacts theupper surface of the upper Ti film 17 in an area inside the opening 31b, and also contacts the Al film 16 at the bottom of the opening 31 a.Therefore, even if the contact resistance of a contact area where theITO film 35 contacts to the Al film 16 directly is high, good electricalcontact between the ITO film 35 and source electrode 13S can beestablished because the ITO film 35 also connects the Al film 16 via theupper Ti film 17.

[0039] Next, a manufacture method of the TFT substrate shown in FIG. 1will be described. A Cr film is formed on the surface of the glasssubstrate 1. This Cr film is patterned to leave the gate electrode 11and external terminal 3. At this time, the control line extending in therow direction is also left. The first insulating film 4 made of SiN isdeposited to a thickness of 400 nm on the surface of the glass substrate1. The first insulating film 4 is deposited through chemical vapordeposition (CVD) using SiH₄ and NH₃ as source gases at a substratetemperature of 320° C.

[0040] An amorphous silicon film is deposited on the surface of thefirst insulating film 4 to a thickness of 30 nm. The amorphous siliconfilm is used as the channel layer 12. The amorphous silicon film isdeposited through CVD using SiH₄ and H₂ as source gas at a substratetemperature of 310° C.

[0041] A SiN film is deposited on the surface of the amorphous siliconfilm to a thickness of 120 nm, and patterned to leave the channelprotective film 18. The SiN film used for the channel protective film 18is deposited through CVD using SiH₄ and NH₃ as source gases at asubstrate temperature of 320° C.

[0042] An n⁺-type amorphous silicon film of 30 nm in thickness, a Tifilm of 20 nm in thickness, an Al film of 100 nm in thickness, and a Tifilm of 20 nm in thickness are sequentially deposited over the wholesurface of the substrate. The amorphous silicon film is depositedthrough CVD using SiH₄ and PH₃ as source gases at a substratetemperature of 250° C. The Ti and Al films are deposited throughsputtering at a room temperature.

[0043] A resist pattern for forming the source and drain electrodes 13Sand 13D is formed on the surface of the uppermost Ti film. By using thisresist pattern as a mask, the lamination structure is etched down to theamorphous silicon film on the first insulating film 4. This etching isperformed by reactive ion etching (RIE) using a mixture gas of Cl₂ andBCl₃. For example, the flow rates of Cl₂ and BCl₃ are both 100 sccm. Ittook about 120 seconds to etch the lamination structure down to theamorphous Si film.

[0044] The channel protective film 18 functions as an etching stopperlayer in a region above the gate electrode 11, so that the etching stopssubstantially at the upper surface of the channel protective film 18.With this etching process, the channel layer 12, source electrode 13S,and drain electrode 13D are formed.

[0045] The second insulating film 30 of SiN is deposited over the wholesurface of the substrate to a thickness of 300 nm. The second insulatingfilm 30 is deposited through CVD using SiH₄ and NH₃ as source gases at asubstrate temperature of 230° C. which is lower than that when the firstinsulating film 4 is deposited.

[0046] The opening 31 b is formed through the second insulating film 30,and at the same time the opening 40 is formed through the first andsecond insulating films 4 and 30. These openings 31 b and 40 are formedthrough RIE using a mixture gas of SF₆ and O₂ under the etchingconditions of SF₆ flow rate of 200 sccm, O₂ flow rate of 200 sccm, and apressure of 10 Pa. Under these etching conditions, the second insulatingfilm is side-etched. The upper Ti film 17 is etched generally in adirection normal to the substrate surface, because of a large impactforce of ions collided with the upper Ti film 17. The inner wall of theopening 31 a in the upper Ti film 17 is therefore retreated from theinner wall of the opening 30 b in the second insulating film 30.

[0047] The first insulating film 4 is deposited at a growth temperaturehigher than that when the second insulating film is deposited.Therefore, the etching rate of the first insulating film 4 is slowerthan that of the second insulating film 30. A difference between theetching rates forms the step on the inner wall of the opening 40.Thereafter, an ITO film is deposited over the whole surface of thesubstrate and patterned to leave the ITO film 35.

[0048] With this manufacture method, good electrical contact between theITO film 35 and source electrode 13S can be established even if the Alfilm 16 is exposed at the bottom of the opening 31 b. It is thereforeunnecessary to make the upper Ti film thick. In the conventional TFTsubstrate shown in FIG. 4, in order to leave the upper Ti film 17 at thebottom of the opening 31, the thickness thereof was set to about 100 nm.If the upper Ti film 17 having a thickness of about 100 nm is used, ittakes about 165 seconds to pattern the lamination structure from theupper Ti film 17 to the channel layer 12. In contrast, in thisembodiment, it is possible to pattern the lamination structure from theupper Ti film 17 to the channel layer 12 in about 120 seconds.

[0049]FIG. 2 is a graph showing a relation between an etching pressureand a lateral etching amount of a SiN film. The abscissa represents anetching pressure in the unit of Pa and the ordinate represents a lateraletching amount in the unit of μm. The etching was performed through RIEusing a mixture gas of SF₆ at a flow rate of 200 sccm and O₂ at a flowrate of 200 sccm. The SiN film etched were formed under the sameconditions as those used for the second insulating film 30 shown in FIG.1, and the first insulating film 4 is disposed under the SiN filmetched. The second insulating film 30 is side-etched while the wholethickness of the first insulating film 4 under the second insulatingfilm 30 is etched.

[0050] As shown in FIG. 2, as the etching pressure rises, the lateraletching amount increases. As the lateral etching amount increases, acontact area between the ITO film 35 and upper Ti film 17 shown in FIG.1 becomes large and the contact resistance can be lowered. In order toestablish good electrical contact between the ITO film 35 and sourceelectrode 13S, it is preferable to set a retract amount of the innerwall of the opening 31 b from the circumferential edge of the opening 31a to 1 μm or larger. However, it is necessary for the outermostcircumferential edge of the opening 31 a not to position outside of theouter edge of the source electrode 13S.

[0051] In this embodiment, although the intermediate layer (Al film 16)of the source and drain electrodes 13S and 13D is made of Al, it may bemade of Al alloy. Although the uppermost layers of the source and drainelectrodes 13S and 13D are made of Ti, they may be made of a differentmaterial which can provide a contact resistance with ITO lower than thatbetween Al and ITO. Such materials may be Mo, Ta, W, oxide of thesemetals, nitride of these metals, and the like.

[0052]FIG. 3 is a partial plan view of a TFT according to the secondembodiment of the invention. On the surface of a glass substrate, aplurality of gate bus lines 11 are disposed extending in the rowdirection. For example, the gate bus line 11 is made of Cr. At one end(right end in FIG. 1) of each gate bus line 11, an inspection gateterminal 22 is disposed, and at the other end, a TAB gate terminal 23 isdisposed. The gate bus line 11 is covered with a gate insulating filmmade of SiN.

[0053] On this gate insulating film, a plurality of drain bus lines 20are disposed extending in the column direction. The drain bus line 20has a three-layer structure of a Ti film/an Al film/a Ti film. At oneend flower end in FIG. 1) of each drain bus line 20, an inspection drainterminal 21 is disposed, and at the other end, a TAB drain terminal 24is disposed.

[0054] At each of cross points between the gate bus lines 11 and drainbus lines 20, a TFT is disposed. A pixel electrode 35 is disposed in anarea surrounded by adjacent two gate bus lines 11 and adjacent two drainbus lines 20. A drain 13D of a TFT 10 is connected to a correspondingdrain bus line 20. A source electrode 13S of TFT 10 is connected to acorresponding electrode 35.

[0055] The gate bus line 11 corresponding to TFT 10 serves also as thegate electrode of TFT 10. A channel protective film 18 disposed for eachTFT covers the channel layer of TFT 10.

[0056] The inspection drain terminal 21 is formed in the same layer bythe same process as the drain bus line 20, and connected to acorresponding drain bus line 20. A terminal protective conductive film35 a is formed over the inspection drain terminal 21, both beingelectrically connected via a contact hole 25 a.

[0057] The inspection gate terminal 22 is formed in the same layer bythe same process as the gate bus line 11, and connected to acorresponding gate bus line 11. A terminal protective conductive film 35b is formed over the inspection gate terminal 22, both beingelectrically connected via a contact hole 25 b. Similar to theinspection gate terminal 22, the terminal protective conductive film 35b is formed over the TAB gate terminal 23.

[0058] The TAB drain terminal 24 is formed in the same layer by the sameprocess as the gate bus line 11. A terminal protective conductive film35 c is also formed over the TAB drain terminal 24, both being connectedvia a contact hole 25 c. The terminal protective conductive film 35 c isconnected to a corresponding drain bus line 20 via a contact hole 26 ata connection part 24A.

[0059] By applying a voltage between one TAB gate terminal 23 and acorresponding inspection gate terminal 22, a conduction failure of thegate bus line 11 can be found. Similarly, a conduction failure of thedrain bus line can be found. By applying a voltage between an inspectiongate 22 and an inspection drain terminal 21, an insulation failuretherebetween can be found.

[0060] The reason why the TAB drain terminal 24 is disposed in the samelayer as the gate bus line 11 is to make the TAB drain terminal 24 andTAB gate terminal 23 have the same lamination structure.

[0061] A cross sectional view taken along one-dot chain line A8-A8corresponds to a TFT shown in FIG. 8. FIG. 4A is a cross sectional viewtaken along one-dot chain line A4-A4 of FIG. 3. A gate insulating film 4covers the surface of a glass substrate 1. On a partial surface area ofthe gate insulating film 4, an amorphous silicon film 12 a is formed. Onthe amorphous silicon film 12 a, the inspection drain terminal 21 isformed. The inspection drain terminal 21 has a lamination structure ofan amorphous silicon film 14 a, a lower Ti film 15 a, an Al film 16 a,and an upper Ti film 17 a, respectively stacked in this order.

[0062] On the gate insulating film 4, a protective insulating film 30 isformed covering the inspection drain terminal 25 a. The contact hole 25s is formed through the protective insulating film. As shown in FIG. 3,this contact hole 25 a is disposed slightly inner than the outerperiphery of the inspection drain terminal 21, and has a ring shapeextending along the outer periphery. Therefore, the protectiveinsulating film 30 is left in the inner area of the contact hole whenthe inspection drain terminal 21 is viewed along a direction normal tothe substrate surface.

[0063] The terminal protective conductive film 35 a is formed on theprotective insulating film 30, covering the inspection drain terminal21. The terminal protective conductive film 35 a is made in contact withthe inspection drain terminal 21 via the contact hole 25 a.

[0064] When the TFT substrate is inspected, a probe is made in contactwith the terminal protective conductive film 35 a on the protectiveinsulating film 30 left in the inner area of the inspection drainterminal 21. Since the protective insulating film 30 is left under thecontact point of the probe, it is possible to prevent the underlyinginspection drain terminal 21 from being damaged by the probe.

[0065]FIG. 4B is a cross sectional view taken along one-dot chain lineB4-B4 shown in FIG. 3. The inspection gate terminal 22 made of Cr isformed on the surface of the glass substrate 1. The gate insulating film4 and protective insulating film 30 are laminated covering theinspection gate terminal 22. The contact hole 25 b is formed through thetwo layers, gate insulating film 4 and protective insulating film 30. Asshown in FIG. 3, the contact hole 26 b is disposed slightly inner thanthe outer periphery of the inspection gate terminal 22, and has a ringshape extending along the outer periphery.

[0066] The terminal protective conductive film 35 b is formed on theprotective insulating film 30, covering the inspection gate terminal 22.The terminal protective conductive film 35 b is connected via thecontact hole 25 b to the inspection gate terminal 22. Similar to theinspection drain terminal 21 shown in FIG. 4A, the gate insulating film4 and protective insulating film 30 are left in the inner area of thecontact hole when the inspection gate terminal 22 is viewed along adirection normal to the substrate surface. It is therefore possible toprevent the underlying inspection gate terminal 22 from being damaged bythe probe.

[0067] Next, a manufacture method of a TFT substrate of the secondembodiment will be described with reference to FIGS. 3 and 8. A Cr filmis formed on the glass substrate 1 and patterned to leave the gate buslines, 11, inspection gate terminals 22, TAB gate terminals 23, and TABdrain terminals 24. A gate insulating film 4 of SiN is deposited to athickness of 400 nm over the surface of the glass substrate 1, coveringthe gate bus lines, 11, inspection gate terminals 22, TAB gate terminals23, and TAB drain terminals 24.

[0068] On the surface of the gate insulating film 4, an amorphoussilicon film is deposited to a thickness of 30 nm. In this filmdeposition, the substrate temperature is set to 310° C. This amorphoussilicon film is patterned by a later process to form the channel layer12. An SiN film is deposited to a thickness of 120 nm on the surface ofthe amorphous silicon film. This SiN film is patterned to leave thechannel protective film 18.

[0069] A method of forming a resist pattern to be used for patterningthe channel protective film 18 will be described. The glass substrate 1is exposed from the bottom (back of the sheet of FIG. 3) by using thegate bus lines 1 1 as a mask to define the boarder along the peripheryof each gate bus line 11. Next, by using an ordinary photomask, theglass substrate 1 is exposed from the bottom to define a boarderperpendicular to each gate bus line 11. After the exposure is performedtwice, the resist mask is developed to form a resist patterncorresponding to the channel protective film 18. By using this resistpattern as a mask, the SiN film is etched to leave the channelprotective film 18. Thereafter, the resist pattern is removed.

[0070] Next, an n⁺-type amorphous silicone film of 30 nm thickness, a Tifilm of 20 nm thickness, an Al film of 100 nm thickness, and a Ti filmof 100 nm thickness are sequentially deposited over the whole substratesurface.

[0071] On the surface of the highest Ti film, a resist patterncorresponding to the source electrode 13S and drain electrode 13D isformed. By using this resist pattern as a mask, the layers down to theamorphous silicon film formed on the gate insulating film 4 are etched.

[0072] In the area above the gate bus line 11, the channel protectivefilm 18 functions as an etching stopper so that the etching generallystops at the upper surface of the channel protective film 18. With thisetching process, the channel layer 12, source electrode 13S, and drainelectrode 13D are formed. At the same time, the drain bus lines 20 andinspection drain terminals 21 shown in FIG. 3 are formed.

[0073] The protective insulating film 30 of SiN is deposited to athickness of 300 nm over the whole substrate surface. This deposition ofthe protective insulating film 30 is performed by the same method as thedeposition of the gate to insulating film 4.

[0074] A contact hole 31 is formed through the protective insulatingfilm 30, and at the same time the contact hole 25 a shown in FIG. 4A andthe contact hole 26 shown in FIG. 3 are formed. At the same time whenthese contact holes are formed, the contact hole 25 b shown in FIG. 4Bis also formed through the first and second insulating films 4 and 30.These contact holes are formed by RIE using a mixture gas of SF₆ and O₂.The etching conditions are an SF₆ flow rate of 200 sccm, an O₂ flow rateof 200 sccm, and a pressure of 10 Pa.

[0075] In the second embodiment, although the contact structure shown inFIG. 8 is used for the connection between the source region of TFT 10and the pixel electrode 35, the structure of the first embodiment shownin FIG. 1 may be used.

[0076]FIG. 5 is a cross sectional view of an inspection drain terminalwherein the contact structure of the first embodiment is used for theconnection between the source region of TFT and the pixel electrode 35.The plan view of a TFT substrate is similar to the plan view of the TFTsubstrate of the second embodiment shown in FIG. 3. In the secondembodiment shown in FIG. 4A, the upper Ti film 17 a is left on thebottom of the contact hole 25 a. In contrast, in the structure shown inFIG. 5, a contact hole 25 aa is formed through the protective insulatingfilm 30 and a contact hole 25 ab is formed through the upper Ti film 17a, similar to the contact holes 31 a and 31 b shown in FIG. 1.

[0077] The side wall of the contact holes 25 aa and 25 ab are formedwith steps similar to the steps on the side wall of the contact holes 31a and 31 b shown in FIG. 1. Therefore, good electrical contact betweenthe terminal protective conductive film 35 a and inspection drainterminal 21 can be realized.

[0078]FIGS. 6A and 6B are plan views of TFT substrates according tofirst and second modifications of the second embodiment. In the secondembodiment, as shown in FIG. 3, the contact hole 25 a has a ring shapeextending along the outer periphery of the inspection drain terminal 21,and the outer and inner peripheries of the contact hole 25 a aregenerally straight lines.

[0079] In the first modification shown in FIG. 6A, in place of thecontact hole 25 a of the second embodiment, a plurality of contact holes26 are disposed. The WE contact holes 26 are discretely disposedslightly inner than the outer periphery of the inspection drain terminal21, and extend along the outer periphery. A cross sectional view takenalong one-dot chain line A5-A5 shown in FIG. 6A is the same as thatshown in FIG. 5. A total sum of lengths of the outer peripheries of thecontact holes 26 is longer than the length of the outer periphery of thecontact hole 25 a shown in FIG. 3. Therefore, the area of the terrace atthe step on the side wall of the contact holes 25 aa and 25 ab shown inFIG. 5 is large. A contact resistance between the terminal protectiveconductive film 35 a and inspection drain terminal 21 can be made lower.Similarly, the contact resistance in the contact area shown in FIG. 3can be made small by forming a plurality of contact holes 26.

[0080] In the second modification shown in FIG. 6B, in place of thecontact hole 25 a shown in FIG. 3, a contact hole 27 is used. The outerand inner peripheries of the contact hole 27 have zigzag patterns.Therefore, similar to the first modification, the area of the terrace atthe step on the side wall of the contact hole can be made large and acontact resistance between the terminal protective conductive film 35 aand inspection drain terminal 21 can be made lower. Similarly, thecontact resistance in the contact area shown in FIG. 3 can be made smallby forming the peripheries of the contact hole 26 in zigzag patterns.

[0081] In the above embodiment, the inspection drain terminal 21 andsource electrode 13S use the Al film and upper Ti film. In place of theAl film, a film made of Cu, Al alloy, or Cu alloy may be used, and inplace of the Ti film, a film made of Ti, Mo, W, Ta, alloy thereof,nitride thereof, or oxide thereof may also be used, with similarexpected advantages of the embodiment.

[0082]FIG. 7 shows an example of a liquid crystal display panel usingthe TFT substrate according to the embodiment of the invention. Aplurality of TFT's 10 are formed on the surface of a glass substrate 1.TFT 10 is covered with a second insulating film 30. An ITO film 35 isformed on the surface of the second insulating film 30 in correspondencewith each TFT 10. An alignment film 50 is formed on the secondinsulating film 30, covering the ITO film 35. A common electrode 61 isformed on the surface of a glass substrate 60, and another alignmentfilm 62 is formed on the surface of the common electrode 61.

[0083] The glass substrates 1 and 60 are disposed with the alignmentfilms 50 and 62 facing each other. Liquid material 70 is filled in a gapbetween the glass substrates 1 and 60. Polarizing films 72 and 73 areplaced on the outer surfaces of the glass substrates 1 and 60. Colorfilters, light shielding films and the like may be disposed, ifnecessary, on the surface of the glass substrate 60.

[0084] The present invention has been described in connection with thepreferred embodiments. The invention is not limited only to the aboveembodiments. It is apparent that various modifications, improvements,combinations, and the like can be made by those skilled in the art.

What is claimed is:
 1. An ITO film contact structure comprising: aconductive film made of Al or alloy containing Al as a main component;an upper conductive film disposed on said conductive film, formed with afirst opening, and made of a material different from Al; an insulatingfilm disposed on said upper conductive film and formed with a secondopening, an inner wall of the second opening being retreated from aninner wall of the first opening; and an ITO film covering a partialupper surface of said insulating film and inner surfaces of the firstand second openings, and contacting a partial upper surface of saidupper conductive film at a region defining a part of the inner wall ofthe second opening.
 2. An ITO film contact structure according to claim1, wherein a contact resistance between a material of said upperconductive film and ITO is smaller than a contact resistance between Aland ITO.
 3. An ITO film contact structure according to claim 2, whereinsaid upper conductive film is made of a material selected from a groupconsisting of Ti, Mo, Ta, W, oxide of these metals, and nitride of thesemetals.
 4. A TFT substrate comprising: an underlying substrate having aninsulating surface; a gate electrode disposed on the insulating surfaceof said underlying substrate; a first insulating film covering theinsulating surface of said underlying substrate and said gate electrode;a channel layer made of semiconductor and disposed on said firstinsulating film, the channel layer overriding said gate electrode; firstand second conductive films made of Al or Al alloy and disposed on anupper surface of said channel layer on both sides of said gateelectrode; a first upper conductive film disposed on said firstconductive film and formed with a first opening; a second upperconductive film disposed on said second conductive film; a secondinsulating film covering said first and second upper conductive filmsand said channel layer and formed with a second opening, an inner wallof the second opening being retreated from an inner wall of the firstopening; and an ITO film covering a partial upper surface of said secondinsulating film and inner surfaces of the first and second openings, andcontacting a partial upper surface of said first upper conductive filmat a region defining a part of the inner surface of the second opening.5. A TFT substrate according to claim 4, further comprising: an externalterminal disposed on the insulating surface of said underlying substrateand made of conductive material, wherein said first and secondinsulating films cover said external terminal, and a third opening isformed through said first and second insulating films, the third openinghaving a bottom defined by a partial upper surface of said externalterminal.
 6. A TFT substrate according to claim 5, wherein an inner wallof the third opening in said second insulating film is retreated from aninner wall of the third opening in said first insulating film.
 7. A TFTsubstrate according to claim 4, wherein said first and second upperconductive films are made of a material selected from a group consistingof Ti, Mo, Ta, W, oxide of these metals, and nitride of these metals. 8.A method of manufacturing a TFT substrate comprising the steps of:forming a gate electrode on a surface of an underlying substrate;forming a first insulating film on the underlying substrate, the firstinsulating film covering the gate electrode; forming a channel layer onthe first insulating film, the channel layer overriding on the gateelectrode, and forming a source electrode and a drain electrode on anupper surface of the channel layer, the source and drain electrodescovering areas on both sides of the gate electrode and including aconductive film made of Al or Al alloy and an upper conductive filmdisposed on the conductive film and made of a material different fromAl; forming a second insulating film on the first insulating film, thesecond insulating film covering the source electrode and the drainelectrode; forming a first opening through the second insulating film inan area corresponding to the source electrode and through the upperconductive film of the source electrode, an inner wall of the firstopening in the second insulating film being retreated from an inner wallof the first opening in the upper conductive film; and forming an ITOfilm on an inner surface of the first opening and on a partial surfaceof the second insulating film.
 9. A method of manufacturing a TFTsubstrate according to claim 8, wherein said first opening forming steppartially etches the second insulating film and the upper conductivefilm under a condition that the second insulating film is etched also ina lateral direction and the upper conductive film is etched only in adirection substantially normal to the surface of the underlyingsubstrate.
 10. A method of manufacturing a TFT substrate according toclaim 8, wherein: said gate electrode forming step includes a step offorming an external terminal on the surface of the underlying substratein an area different from an area where the gate electrode is formed;said first insulating film forming step covers the external terminalwith the first insulating film; said second insulating film forming stepforms the second insulating film on the first insulating film over theexternal terminal; and said first opening forming step includes a stepof forming a second opening through the first and second insulatingfilms in an area corresponding to the external terminal.
 11. A method ofmanufacturing a TFT substrate according to claim 10, wherein the firstand second insulating films are made of SiN, and the second insulatingfilm is formed at a substrate temperature higher than a substratetemperature used when the first insulating film is formed.
 12. A thinfilm transistor substrate comprising: a substrate having a principalsurface; a plurality of thin film transistors formed on the principalsurface of said substrate, each thin film transistor including a gateelectrode, a channel layer, a source electrode and a drain electrode; afirst terminal formed on the principal surface of said substrate, saidfirst terminal being connected to one of the gate electrode and thedrain electrode of at least one thin film transistor; a protectiveinsulating film formed on the principal surface of said substrate,covering the plurality of thin film transistors and said fist terminal;a first contact hole formed, at a position corresponding to the sourceelectrode of each thin film transistor, through said protectiveinsulating film to an upper surface of the source electrode; a pixelelectrode formed on said protective insulating film in correspondencewith each thin film transistor, said pixel electrode being connected tothe source electrode of a corresponding thin film transistor via saidfirst contact hole; a second contact hole formed, at a positioncorresponding to said first terminal, through said protective insulatingfilm to an upper surface of said first terminal, said second contacthole being disposed so that said protective insulating film is left inan inner area of said first terminal as viewed along a direction normalto the principal surface of said substrate; and a first terminalprotective conductive film formed on said protective insulating film,said first terminal protective conductive film being connected to saidfirst terminal via said second contact hole, covering said protectiveinsulating film left in the inner area of said first terminal, and beingmade of material same as material of said pixel electrode.
 13. A thinfilm transistor according to claim 12, wherein said second contact holeis disposed inner than an outer periphery of said first terminal asviewed along the direction normal to the principal surface of saidsubstrate, and extends along the outer periphery.
 14. A thin filmtransistor according to claim 12, further comprising: a second terminaldisposed between the principal surface of said substrate and saidprotective insulating film and connected to the other of the gateelectrode and the drain electrode of at least one thin film transistor;a third contact hole formed, at a position corresponding to said secondterminal, through said protective insulating film to an upper surface ofsaid second terminal, said third contact hole being disposed so thatsaid protective insulating film is left in an inner area of said secondterminal as viewed along the direction normal to the principal surfaceof said substrate; and a second terminal protective conductive filmformed on said protective insulating film, said second terminalprotective conductive film being connected to said second terminal viasaid third contact hole, covering said protective insulating film leftin the inner area of said second terminal, and being made of materialsame as material of said pixel electrode.
 15. A thin film transistoraccording to claim 14, wherein: said thin film transistor is aninversely staggered type thin film transistor wherein the channel layeris disposed over the gate electrode, and further comprises a gateinsulating film between the gate electrode of said thin film transistorand the channel layer; the source electrode includes at least a firstconductive layer and a second conductive layer formed on the firstconductive layer; said first contact hole is also formed through thesecond conductive layer, and a side wall of said first contact has astep defined by a portion of an upper surface of the first conductivelayer; said pixel electrode is in contact with an upper surface of thesecond conductive layer at the step on the side wall of said firstcontact hole; said first terminal is connected to the drain electrode ofsaid thin film transistor and includes at least a first conductive layerand a second conductive layer same as the first and second conductivelayers of the source electrode; said second contact hole is also formedthrough the second conductive layer of said first terminal, and a sidewall of said second contact has a step defined by a portion of an uppersurface of the first conductive layer; and said first terminalprotective conductive film is in contact with an upper surface of thesecond conductive film at the step on the side wall of said secondcontact hole.
 16. A thin film transistor according to claim 15, whereinthe first and second conductive layers and said pixel electrode are madeof material so that a contact resistance between said pixel electrodeand the second conductive layer is lower than a contact resistancebetween the pixel electrode and the first conductive layer.
 17. A thinfilm transistor according to claim 15, wherein said second contact holeincludes a plurality of contact holes discretely distributed.
 18. A thinfilm transistor according to claim 15, wherein a boarder shape of saidsecond contact hole includes a zigzag pattern as viewed along thedirection normal to the principal surface of said substrate.
 19. A thinfilm transistor substrate comprising: a substrate having a principalsurface; a plurality of thin film transistors formed on the principalsurface of said substrate, each thin film transistor including a gateelectrode, a channel layer, a source electrode and a drain electrode,said thin film transistor being an inversely staggered type thin filmtransistor; a contact area formed on the principal surface of saidsubstrate, said contact area being connected to the drain electrode ofat least one thin film transistor and includes at least a firstconductive film and a second conductive film formed on the firstconductive film; a protective insulating film formed on the principalsurface of said substrate, covering said thin film transistor and saidcontact area; a first contact hole formed, at a position correspondingto the source electrode of each thin film transistor, through saidprotective insulating film; a pixel electrode formed on said protectiveinsulating film in correspondence with each thin film transistor, saidpixel electrode being connected to the source electrode of acorresponding thin film transistor via said first contact hole; a secondcontact hole formed, at a position corresponding to said contact area,through said protective insulating film and said second conductive film,said second contact hole having a step defined by a portio of an uppersurface of the second conductive film; and a terminal conductive filmformed on said protective conductive film in correspondence with saidcontact area, said terminal conductive film being connected to saidcontact area via said second contact hole, and electrically connected toan upper surface of the second conductive film defining the step on theside wall of said second contact hole.
 20. A thin film transistoraccording to claim 19, wherein the first and second conductive layersand said pixel electrode are made of material so that a contactresistance between said pixel electrode and the second conductive layeris lower than a contact resistance between the pixel electrode and thefirst conductive layer.
 21. A thin film transistor according to claim19, wherein said second contact hole includes a plurality of contactholes discretely distributed.
 22. A thin film transistor according toclaim 19, wherein a boarder shape of said second contact hole includes azigzag pattern as viewed along the direction normal to the principalsurface of said substrate.